1. Field of the Invention
The present invention relates to technologies for inspecting fine circuit patterns for semiconductor devices or LCDs on a substrate, particularly such circuit patterns on a semiconductor wafer. More specifically, the invention relates to such inspecting technologies whereby the circuit patterns formed on a semiconductor wafer are irradiated with light, laser light, or a charged-particle beam to obtain an exterior image of the wafer.
2. Background Art
Semiconductor devices are typically manufactured by repeating the steps of forming a circuit pattern on a semiconductor wafer using a photomask and then transferring the pattern on the semiconductor wafer by lithography and etching. During the manufacture of semiconductor devices, the quality of individual processes including the aforementioned lithography and etching processes, as well as the presence of foreign matter during the manufacturing steps, have a significant influence on the yield or the like of the final semiconductor device products. For this reason, it is important in the manufacture of semiconductor devices to detect or prevent abnormality in each step or the development of defects as early as possible. Thus, during the manufacture of semiconductor devices, the circuit pattern formed on the semiconductor wafer is inspected in each manufacturing step.
Various inspection apparatuses are used during the manufacture of semiconductor devices. One example is an optical exterior inspection apparatus that determines the presence of abnormality using an optical image obtained by irradiating the pattern with laser light or the like. Another example is an electron beam inspection apparatus whereby the pattern is scanned with a charged-particle beam, such as an electron beam, to acquire an image based on the intensity of signals of the secondary electrons or reflected electrons that are produced, wherein the presence of abnormality is determined using such image. Such various inspection apparatuses are actually being used for the inspection of circuit patterns.                Patent Document 1: JP Patent Publication (Kokai) No. 5-258703 A (1993)        Patent Document 2: U.S. Pat. No. 5,502,306        Patent Document 3: JP Patent Publication (Kokai) No. 59-160948 A (1984)        